RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 23 POWER-ON-RESET CIRCUIT 23.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 23-1. VDD Figure 23-1. Block Diagram of Power-on-reset Circuit Reference voltage source 23.3 Operation of Power-on-reset Circuit + - VDD Internal reset signal An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPDR = 1.51 V 0.03 V), the reset status is released. The supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.03 V) are compared. When VDD < VPDR, the internal reset signal is generated. The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below. R01UH0317EJ0004 Rev. 0.04 1109 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 23 POWER-ON-RESET CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/2) (1) When LVD is OFF (option byte 000C1H/020C1H: VPOC2 = 1B) Supply voltage (VDD) Note 1 2.7 V VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) High-speed on-chip oscillator clock (fIH) High-speed system clock (fMX) (when X1 oscillation is selected) CPU 0 V Internal reset signal Operation stops Wait for oscillation Note 2 accuracy stabilization Starting oscillation is specified by software (High-speed on-chip Note 3 oscillator clock) Wait for oscillation Note 2 accuracy stabilization Starting oscillation is specified by software Note 4 Reset processing Normal operation Reset period Reset processing (oscillation stop) Note 4 Normal operation (High-speed on-chip Note 3 oscillator clock) Operation stops Notes 1. The operation guaranteed range is 2.7 V VDD 5.5 V. To make the state at lower than 2.7 V reset state when the supply voltage falls, use the reset function of the voltage detector, or input the low level to the RESET pin. 2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 3. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. 4. Reset processing time: 265 to 407 μ s Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0317EJ0004 Rev. 0.04 1110 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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