RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR CHAPTER 17 SOUND GENERATOR The Sound Generator generates an audio-frequency tone signal and a high-frequency pulse-width modulated (PWM) signal. The duty cycle of the PWM signal defines the volume. By default, the two signal components are routed to separate pins. But both signals can also be combined to generate a composite signal that can be used to drive a loudspeaker circuit. 17.1 Overview The Sound Generator consists of a programmable square wave tone generator and a programmable pulse-width modulator. Features Programmable sound frequency Activation of the automatic logarithmic decrement function for linear volume decreasing without CPU instruction Programmable volume level (9 bit resolution) Wide range of PWM signal frequency Sound can be stopped or retriggered (even if ALD is switched on) Composite or separated frequency/volume output for external circuitry variation Variable PWM level for generation of the SGTIO interrupt (noise dependent end interrupt) Hardware-optimized update of frequency and volume to avoid audible artifacts R01UH0317EJ0004 Rev. 0.04 997 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR 17.1.1 Description The following figure provides a functional block diagram of the Sound Generator. INTSG0 fSG0CLK Note SG0FL frequency low register ≤ SG0ITH ? Y SG0CTL.PWR SG0ITH interrupt threshold register 1 0 Auto Logarithmic Decrement Figure 17-1. Sound Generator Block Diagram Clear 9-bit S0GFL frequency counter SG0FL frequency compare buffer Match Match SG0PWM volume compare buffer 1 0 CPU write to SG0PWM Load Load SG0PWM volume register 0 1 fPWM (32 to 64 kHz) & & 8-bit SG0SDF auto-decrement counter R01UH0317EJ0004 Rev. 0.04 998 Feb. 22, 2013 Load fDecrement SG0CTL.ALDS = 0? Clear 9-bit S0GFH tone counter Match SG0FH tone compare buffer SG0FH frequency high register fPWM (32 to 64 kHz) Y Tone S RS-FF R Reset PWM /2 2 × fTone (200 Hz to 12 kHz) SG0SDF sound duration register Note The Sound Generator's input clock frequency fSG0CLK is fCLK or fCLK/2. Refer the table below. fCLK fSG0CLK 32 MHz fCLK/2 16 MHz 24 MHz fCLK 24 MHz 16 MHz fCLK 16 MHz 8 MHz fCLK 8 MHz 4 MHz fCLK 4 MHz & fTone (100 Hz to 6 kHz) SG0OF SG0 SG0CTL.OS SG0OA fPWM (min. 32 kHz) Tone generator The tone generator consists of two up-counters with compare registers. The values written to the frequency registers are automatically copied to compare buffers. The counters are reset to zero when their values match the contents of the associated compare buffers. The 9-bit counter S0GFL generates a clock with a frequency between 32 kHz and 64 kHz. This clock constitutes the PWM frequency. It is also the input of the second 9-bit counter S0GFH. The resulting tone signal behind the by-two-divider has a frequency between 250 Hz and 6 kHz and a 50 % duty cycle. 0 1 SGO SG0A
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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