RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
Figure 14-35. Format of CAN Module Interrupt Enable Register (C0IE, C1IE) (2/2)
Set CIE3 Clear CIE3 Setting of CIE3 Bit
0 1 CIE3 bit is cleared to 0.
1 0 CIE3 bit is set to 1.
Other than above CIE3 bit is not changed.
Set CIE2 Clear CIE2 Setting of CIE2 Bit
0 1 CIE2 bit is cleared to 0.
1 0 CIE2 bit is set to 1.
Other than above CIE2 bit is not changed.
Set CIE1 Clear CIE1 Setting of CIE1 Bit
0 1 CIE1 bit is cleared to 0.
1 0 CIE1 bit is set to 1.
Other than above CIE1 bit is not changed.
Set CIE0 Clear CIE0 Setting of CIE0 Bit
0 1 CIE0 bit is cleared to 0.
1 0 CIE0 bit is set to 1.
Other than above CIE0 bit is not changed.
R01UH0317EJ0004 Rev. 0.04 860
Feb. 22, 2013