RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
14.12 Interrupt Function
The CAN module provides 6 different interrupt sources.
The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals
are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt
sources is generated, the interrupt sources can be identified by using an interrupt status register. After an interrupt source
has occurred, the corresponding interrupt status bit must be cleared to 0 by software.
No. Interrupt Status Bit Interrupt Enable Bit
1 CINTS0 Not
e
2 CINTS1 Not
e
Name Register Name Register
Table 14-20. List of CAN Module Interrupt Sources
Interrupt
Request Signal
Interrupt Source Description
C0INTS CIE0 Note C0IE INTC0TRX Message frame successfully transmitted
from message buffer m
C0INTS CIE1 Note C0IE INTC0REC Valid message frame reception in
message buffer m
3 CINTS2 C0INTS CIE2 C0IE INTC0ERR CAN module error state interrupt
(Supplement 1)
4 CINTS3 C0INTS CIE3 C0IE CAN module protocol error interrupt
(Supplement 2)
5 CINTS4 C0INTS CIE4 C0IE
CAN module arbitration loss interrupt
6 CINTS5 C0INTS CIE5 C0IE INTC0WUP CAN module wakeup interrupt from CAN
sleep mode (Supplement 3)
Note The IE bit (message buffer interrupt enable bit) in the C0MCTRLm register of the corresponding message buffer
has to be set to 1 for that message buffer to participate in the interrupt generation process.
Supplements 1. This interrupt is generated when the transmission/reception error counter is at the warning level, or in
the error passive or bus-off state.
2. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs.
3. This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a
falling edge is detected at the CAN reception pin (CAN bus transition from recessive to dominant).
Remark m = 0 to 15
R01UH0317EJ0004 Rev. 0.04 904
Feb. 22, 2013