RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10) (2/2) (ii) During operation (SEmn = 1) (lower 8 bits: SDRpL) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Receive data register (Write FFH as dummy data.) SDRpL Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10) : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user (2) Operation procedure Figure 12-35. Initial Setting Procedure for Master Reception Starting initial setting Setting PER0 register Setting SPSm register Setting SMRmn register Setting SCRmn register Setting SDRmn register Setting SOm register Setting port Writing to SSm register Starting communication Release the serial array unit from the reset status and start clock supply. Set the operation clock. Set an operation mode, etc. Set a communication format. Set a transfer baud rate. Manipulate the CKOmn bit and set an initial output level. Enable clock output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 to set SEmn = 1. Set dummy data to the SDRmn register and start communication. Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks have elapsed. R01UH0317EJ0004 Rev. 0.04 603 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-36. Procedure for Stopping Master Reception Starting setting to stop Setting STm register Stopping communication Write 1 to the STmn bit of the target channel. Stop communication in midway. Remark Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm register (see Figure 12-37 Procedure for Resuming Master Reception). R01UH0317EJ0004 Rev. 0.04 604 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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