RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 7 REAL-TIME CLOCK Figure 7-26. Operation when (DEV, F12, F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0) 7FFFH-24H (36) 7FFFH-24H (36) Count start 0000H 7FDAH 7FDBH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 7FDAH 7FDBH 0000H 0001H 7FFFH Subcount register (16-bit) count value 59 00 40 20 39 19 SEC 00 01 R01UH0317EJ0004 Rev. 0.04 483 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 8 INTERVAL TIMER 8.1 Functions of Interval Timer CHAPTER 8 INTERVAL TIMER An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP Mode. 8.2 Configuration of Interval Timer The interval timer includes the following hardware. Table 8-1. Configuration of Interval Timer Item Configuration Counter 15-bit counter Control registers fSUB fIL fMX/122 fMX/128 fMX/244 fMX/256 fIH/122 fIH/128 fIH/244 fIH/256 Selector RTCCL7, 6, RTCCK1, 0 Peripheral enable register 0 (PER0) RTC clock selection register (RTCCL) Interval timer control register (ITMC) Figure 8-1. Block Diagram of Interval Timer RINTE Count clock Internal bus 15-bit counter Match singnel ITMCMP14-ITMCMP0 Interval timer control register (ITMC) R01UH0317EJ0004 Rev. 0.04 484 Feb. 22, 2013 Clear Interrupt signal (INTIT)
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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