RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
5.7.4 Example of controlling Peripheral clock
In this product, the unnecessary macro clock is stopped in the root for low power consumption and noise attenuation.
The special control registers are configured for the purpose.
Moreover, PCKSEL controls the selection and supply of the operation clock for the asynchronous macro CAN, but
the clock selection bit of SG macro is also in this register, bit0 (SGCLKSEL) in order to save address resources.
Peripheral enable register0 (PER0)
Symbol 7 6 5 4 3 2 1 0
PER0 RTCEN LIN1EN LIN0EN SAU1EN SAU0EN TAU2EN TAU1EN TAU0EN
Reset init value 0 0 0 0 0 0 0 0
R/W (hardware) R/W R/W R/W R/W R/W R/W R/W R/W
R/W (user) R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral enable register1 (PER1)
Symbol 7 6 5 4 3 2 1 0
PER1 ADCEN 0 MTRCEN SGEN 0 0 0 0
Reset init value 0 0 0 0 0 0 0 0
R/W (hardware) R/W R R/W R/W R R R R
R/W (user) R/W R R/W R/W R R R R
Peripheral clock select register (PCKSEL)
Symbol 7 6 5 4 3 2 1 0
PCKSEL 0 CAN CAN CAN CAN 0 0 SGCLK
MCKE1 MCK1 MCKE0 MCK0
SEL
Reset init value 0 0 0 0 0 0 0 0
R/W (hardware) R R/W R/W R/W R/W R R R/W
R/W (user) R R/W R/W R/W R/W R R R/W
Control contents of PER0,1
Bit value Control contents
0 Stops the input clock supply to peripheral macro.
SFR of peripheral macro can’t be written. (read possible)
Peripheral macro is in reset status.
1 Supplies the input clock to peripheral macro.
SFR of peripheral macro can be written.
The LCD macro connects directly with fIL, fSUB, and fMAIN, and becomes an asynchronization macro like CAN macro.
Inside LCD macro, SCOC bit is used to control LCD sub clock, the low power consumption has been taken into account to
LCD source clock division, so the chip peripheral clock control bit PER/PCKSEL is not configured for LCD macro.
R01UH0317EJ0004 Rev. 0.04 301
Feb. 22, 2013