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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 24 VOLTAGE DETECTOR<br />

24.4 Operation of Voltage Detector<br />

24.4.1 When used as reset mode<br />

When starting operation<br />

Start in the following initial setting state.<br />

Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by<br />

using the option byte 000C1H/020C1H.<br />

Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level<br />

register (LVIS))<br />

When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H.<br />

Bit 7 (LVIMD) is 1 (reset mode).<br />

Bit 0 (LVILV) is 1 (low-voltage detection level: VLVD).<br />

Figure 24-4 shows the timing of the internal reset signal generated by the voltage detector.<br />

R01UH0317EJ0004 Rev. 0.04 1120<br />

Feb. 22, 2013

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