RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 23 POWER-ON-RESET CIRCUIT
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (1/2)
(1) When LVD is OFF (option byte 000C1H/020C1H: VPOC2 = 1B)
Supply voltage
(VDD)
Note 1 2.7 V
VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
High-speed on-chip
oscillator clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
CPU
0 V
Internal reset signal
Operation
stops
Wait for oscillation
Note 2
accuracy stabilization
Starting oscillation is
specified by software
(High-speed on-chip
Note 3
oscillator clock)
Wait for oscillation
Note 2
accuracy stabilization
Starting oscillation is
specified by software
Note 4
Reset processing Normal operation
Reset
period
Reset processing
(oscillation
stop)
Note 4
Normal operation
(High-speed on-chip
Note 3
oscillator clock)
Operation stops
Notes 1. The operation guaranteed range is 2.7 V VDD 5.5 V. To make the state at lower than 2.7 V reset state
when the supply voltage falls, use the reset function of the voltage detector, or input the low level to the
RESET pin.
2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip
oscillator clock.
3. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
4. Reset processing time: 265 to 407 μ s
Remark VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
R01UH0317EJ0004 Rev. 0.04 1110
Feb. 22, 2013