RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 24 VOLTAGE DETECTOR
(1) Voltage detection register (LVIM)
This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as
well as to check the LVD output mask status.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 24-2. Format of Voltage Detection Register (LVIM)
Address: FFFA9H After reset: 00H Note 1 Note 2
R/W
Symbol 6 5 4 3 2
LVIM LVISEN 0 0 0 0 0 LVIOMSK LVIF
LVISEN Specification of whether to enable or disable rewriting the voltage detection level
register (LVIS)
0 Disabling rewriting
Note 3
1 Enabling rewriting
LVIOMSK Mask status flag of LVD output
0 Mask is invalid
Note 4
1 Mask is valid
LVIF Voltage detection flag
0 Supply voltage (VDD) detection voltage (VLVD), or when LVD operation is disabled
1 Supply voltage (VDD) < detection voltage (VLVD)
Notes 1. The reset value changes depending on the reset source.
If the LVIS register is reset by LVD, it is not reset but holds the current value. In other reset, LVISEN is
cleared to 0.
2. Bit 0 and 1 are read-only.
3. This can only be set when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the
option byte (In the other mode is invalid).
4. LVIOMSK bit is automatically set to “1” in the following periods and reset or interruption by LVD is
masked.
Period during LVISEN = 1
Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes stable
Waiting period from the time when the value of LVILV bit changes until LVD detection voltage becomes
stable
R01UH0317EJ0004 Rev. 0.04 1116
Feb. 22, 2013