RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1281 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F0043 - - - - F0045 - - - - F0046 - - - - F0047 - - - - F004D - - - - F0050 - - - - F0051 - - - - F0053 - - - - F0055 - - - - F0057 - - - - F0058 - - - - F0059 - - - - F005D - - - - F0060 - - - - F0061 PIM3 (Port intput mode register 3) E E - R R R R R R E R PIM3_1 - - - - - - E - PIM5 (Port intput mode register 5) E E - E E E R R E E E PIM5_7 PIM5_6 PIM5_5 PIM5_2 PIM5_1 PIM5_0 E E E - - E E E PIM6 (Port intput mode register 6) E E - R R R R E R E R PIM6_3 PIM6_1 - - - - E - E - PIM7 (Port intput mode register 7) E E - R R R R R R R E PIM7_0 - - - - - - - E PIM13 (Port intput mode register 13) E E - R R E R R R R R PIM13_5 - - E - - - - - LCDPF0 (LCD port function register 0) E E - E E E E E E E E LCDPF0_7 LCDPF0_6 LCDPF0_5 LCDPF0_4 LCDPF0_3 LCDPF0_2 LCDPF0_1 LCDPF0_0 E E E E E E E E LCDPF1 (LCD port function register 1) E E - E E E E E E E E LCDPF1_7 LCDPF1_6 LCDPF1_5 LCDPF1_4 LCDPF1_3 LCDPF1_2 LCDPF1_1 LCDPF1_0 E E E E E E E E LCDPF3 (LCD port function register 3) E E - E E E E E E E E LCDPF3_7 LCDPF3_6 LCDPF3_5 LCDPF3_4 LCDPF3_3 LCDPF3_2 LCDPF3_1 LCDPF3_0 E E E E E E E E LCDPF5 (LCD port function register 5) E E - E E E E E E E E LCDPF5_7 LCDPF5_6 LCDPF5_5 LCDPF5_4 LCDPF5_3 LCDPF5_2 LCDPF5_1 LCDPF5_0 E E E E E E E E LCDPF7 (LCD port function register 7) E E - R R E E E E R R LCDPF7_5 LCDPF7_4 LCDPF7_3 LCDPF7_2 - - E E E E - - LCDPF8 (LCD port function register 8) E E - E E E E E E E E LCDPF8_7 LCDPF8_6 LCDPF8_5 LCDPF8_4 LCDPF8_3 LCDPF8_2 LCDPF8_1 LCDPF8_0 E E E E E E E E LCDPF9 (LCD port function register 9) E E - E E E E E E E E LCDPF9_7 LCDPF9_6 LCDPF9_5 LCDPF9_4 LCDPF9_3 LCDPF9_2 LCDPF9_1 LCDPF9_0 E E E E E E E E LCDPF13 (LCD port function register 13) E E - R E R R R R R R LCDPF13_6 - E - - - - - - TNFEN0 (Noise filter enable register for each channel of TAU unit0) E E - E E E E E E E E TNFEN0_7 TNFEN0_6 TNFEN0_5 TNFEN0_4 TNFEN0_3 TNFEN0_2 TNFEN0_1 TNFEN0_0 E E E E E E E E TNFSMP0 (Sampling clock select of noise filter for unit0 (2set)) E E - E E E E E E E E TNFSMP013 TNFSMP012 TNFSMP011 TNFSMP010 TNFSMP003 TNFSMP002 TNFSMP001 TNFSMP000 E E E E E E E E 1281 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1282 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F0062 - - - - F0064 - - - - F0065 - - - - F0066 - - - - F0068 - - - - F0069 - - - - F006A TNFCS0 (Noise filter clock select register for each channel of TAU unit0) E E - E E E E E E E E TNFCS0_7 TNFCS0_6 TNFCS0_5 TNFCS0_4 TNFCS0_3 TNFCS0_2 TNFCS0_1 TNFCS0_0 E E E E E E E E TNFEN1 (Noise filter enable register for each channel of TAU unit1) E E - E E E E E E E E TNFEN1_7 TNFEN1_6 TNFEN1_5 TNFEN1_4 TNFEN1_3 TNFEN1_2 TNFEN1_1 TNFEN1_0 E E E E E E E E TNFSMP1 (Sampling clock select of noise filter for unit1 (2set)) E E - E E E E E E E E TNFSMP113 TNFSMP112 TNFSMP111 TNFSMP110 TNFSMP103 TNFSMP102 TNFSMP101 TNFSMP100 E E E E E E E E TNFCS1 (Noise filter clock select register for each channel of TAU unit1) E E - E E E E E E E E TNFCS1_7 TNFCS1_6 TNFCS1_5 TNFCS1_4 TNFCS1_3 TNFCS1_2 TNFCS1_1 TNFCS1_0 E E E E E E E E TNFEN2 (Noise filter enable register for each channel of TAU unit2) E E - E E E E E E E E TNFEN2_7 TNFEN2_6 TNFEN2_5 TNFEN2_4 TNFEN2_3 TNFEN2_2 TNFEN2_1 TNFEN2_0 E E E E E E E E TNFSMP2 (Sampling clock select of noise filter for unit2(2set)) E E - E E E E E E E E TNFSMP213 TNFSMP212 TNFSMP211 TNFSMP210 TNFSMP203 TNFSMP202 TNFSMP201 TNFSMP200 E E E E E E E E TNFCS2 (Noise filter clock select register for each channel of TAU unit2) E E - E E E E E E E E TNFCS2_7 TNFCS2_6 TNFCS2_5 TNFCS2_4 TNFCS2_3 TNFCS2_2 TNFCS2_1 TNFCS2_0 E E E E E E E E - - - - F006E ADPC (A/D port configuration register) - E - - - - - - - - - - - - - F006F - - - - F0070 - - - - F0071 - - - - F0072 - - - - F0073 - - - - F0074 - - - - F0075 POM (Port output mode register) E E - R R E E E E E E POM_5 POM_4 POM_3 POM_2 POM_1 POM_0 - - E E E E E E TIS00 (Timer input select register 00) E E - E E R E E E R E TIS031 TIS030 TIS020 TIS011 TIS010 TIS000 E E - E E E - E TIS01 (Timer input select register 01) E E - E E R E E E R E TIS071 TIS070 TIS060 TIS051 TIS050 TIS040 E E - E E E - E TIS10 (Timer input select register 10) E E - E E R E E E R R TIS131 TIS130 TIS120 TIS111 TIS110 E E - E E E - - TIS11 (Timer input select register 11) E E - E E E E E E E E TIS171 TIS170 TIS161 TIS160 TIS151 TIS150 TIS141 TIS140 E E E E E E E E TIS20 (Timer input select register 20) E E - E E E E E E E E TIS231 TIS230 TIS221 TIS220 TIS211 TIS210 TIS201 TIS200 E E E E E E E E TIS21 (Timer input select register 21) E E - E E E E E E E E TIS271 TIS270 TIS261 TIS260 TIS251 TIS250 TIS241 TIS240 E E E E E E E E 1282 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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