RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Figure 14-65. Message Buffer Initialization No START RDY = 1? Yes Clear RDY bit RDY = 0? Yes Set C0MCONFm register Set C0MIDHm register, C0MIDLm register Transmit message buffer? Yes Set C0MDLCm register Clear C0MDBm register Set C0MCTRLm register Set RDY bit END Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared. 2. Make the following settings for message buffers not used by the application. - Clear the RDY, TRQ, and DN bits of the C0MCTRLm register to 0. - Clear the MA0 bit of the C0MCONFm register to 0. R01UH0317EJ0004 Rev. 0.04 921 Feb. 22, 2013 No No
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Figure 14-66 shows the processing for a receive message buffer (MT [2:0] bits of C0MCONFm register = 001B to 101B). Figure 14-66. Message Buffer Redefinition No START Clear VALID bit RDY = 1? Yes Clear RDY bit RDY = 0? RSTAT = 0 or Note 1 VALID = 1? Set message buffers Set RDY bit END R01UH0317EJ0004 Rev. 0.04 922 Feb. 22, 2013 Yes Yes Note 2 Wait for 4 CAN data bits Notes 1. Confirm that a message is being received because RDY bit must be set after a message is completely received. 2. Avoid message buffer redefinition during store operation of message reception by waiting additional 4 CAN data bits. No No
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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RL78/D1A User’s Manual: Hardware
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