RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE Figure 3-38. Example of ES:[HL + byte], ES:[DE + byte] OP code byte ES rp (HL/DE) Target memory Memory Figure 3-39. Example of ES:word[B], ES:word[C] OP code Low Addr. High Addr. OP code Low Addr. High Addr. ES r (B/C) Target memory Memory Figure 3-40. Example of ES:word[BC] ES rp (BC) Target memory Memory FFFFFH 00000H FFFFFH 00000H FFFFFH 00000H R01UH0317EJ0004 Rev. 0.04 141 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address. [Operand format] Identifier Description [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable) ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register) OP code OP code Figure 3-41. Example of [HL+B], [HL+C] rp (HL) r (B/C) Target memory Memory Figure 3-42 Example of ES:[HL+B], ES:[HL+C] ES rp (HL) r (B/C) Target memory Memory FFFFFH F0000H FFFFFH 00000H R01UH0317EJ0004 Rev. 0.04 142 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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33.3.2 High speed on chip oscillato
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RL78/D1A User’s Manual: Hardware
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