RL78/D1A User's Manual: Hardware - Renesas

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Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 11 A/D CONVERTER
11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)
In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not stop in this status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Figure 11-25. Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
ADCE
Hardware
trigger
The trigger is not
acknowledged.
ADCS
ADS
A/D
conversion
status
ADCR,
ADCRH
INTAD
Stop
status
ADCE is set to 1.
ADCS is set to 1.
Trigger
standby
status
Conversion
standby
A hardware trigger
is generated.
ANI0 to ANI3
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 2
(ANI2)
Data 1
(ANI1)
Data 3
(ANI3)
Data 2
(ANI2)
Data 0 Data 1
(ANI0) (ANI1)
Data 3
(ANI3)
A hardware trigger is
generated during A/D
conversion operation.
A/D conversion
ends and the next
conversion starts.
Conversion is
interrupted
and restarts.
ANI4 to ANI7
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Data 0
(ANI0)
Data 1
(ANI1)
Data 0 (ANI0)
Data 2
(ANI2)
Data 3 Data 0
(ANI3) (ANI0)
Data 1 Data 2 Data 3
(ANI1) (ANI2) (ANI3)
ADS is rewritten during
A/D conversion operation.
Data 1
(ANI1)
ADCE is cleared to 0.
R01UH0317EJ0004 Rev. 0.04 537
Feb. 22, 2013
Data 4
(ANI4)
Data 0
(ANI0)
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
Data 5
(ANI5)
Data 4
(ANI4)
Data 6
(ANI6)
Data 5
(ANI5)
Data 7
(ANI7)
Data 6
(ANI6)
ADCS is overwritten
with 1 during A/D
conversion operation.
Data 4
(ANI4)
Data 7
(ANI7)
Data 5
(ANI5)
Data 4
(ANI4)
Data 6
(ANI6)
Data 4
(ANI4)
Data 5
(ANI5)
Data 5
(ANI5)
Data 4
(ANI4)
ADCS is cleared to 0
during A/D conversion
operation.
Data 6
(ANI6)
Data 5
(ANI5)
Data 7
(ANI7)
Data 6
(ANI6)
Data 4
(ANI4)
Trigger The trigger
standby is not
status acknowledged.
Conversion is
interrupted.
Conversion
standby
Data 7
(ANI7)
Stop
status