RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER
(2) Compare registers for sine side (MCMPk0) (k = 1 to 4)
The 8-bit MCMPk0 registers hold the values that define the PWM pulse width for the sine side of the connected
meters.
The contents of the registers are continuously compared to the timer counter value:
Registers MCMP10 to MCMP40 are compared to CNT0.
When the register contents match the timer counter contents, a match signal is generated. Thus a PWM pulse with a
pulse width corresponding to the MCMPk0 register contents is output to the sine side of the connected meter.
These registers can be read/written in 8-bit units.
This register is cleared by any reset.
Address: F0162H, F0164H, F0166H, F0168H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
MCMPk0 sine DATA
Remarks 1. New data must only be written to registers MCMPk0 if the corresponding bit MCMPCk.TEN = 0.
2. Don't write to the compare register MCMPk0, until the corresponding bit MCMPCk.TEN has been reset to
0 automatically.
3. To enable master-to-slave register copy upon next CNTm overflow set MCMPCk.TEN = 1.
(3) Compare registers for cosine side (MCMPk1) (k = 1 to 4)
The 8-bit MCMPk1 registers hold the values that define the PWM pulse width for the cosine side of the connected
meters.
The contents of the registers are continuously compared to the timer counter value:
Registers MCMP11 to MCMP41 are compared to CNT0.
When the register contents match the timer counter contents, a match signal is generated. Thus a PWM pulse with a
pulse width corresponding to the MCMPk1 register contents is output to the cosine side of the connected meter.
These registers can be read/written in 8-bit units.
This register is cleared by any reset.
Address: F0163H, F0165H, F0167H, F0169H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
MCMPk1 cosine DATA
Remarks 1. New data must only be written to registers MCMPk1 if the corresponding bit MCMPCk.TEN = 0.
2. Don't write to the compare register MCMPk1, until the corresponding bit MCMPCk.TEN has been reset to
0 automatically.
3. To enable master-to-slave register copy upon next CNTm overflow set MCMPCk.TEN = 1.
R01UH0317EJ0004 Rev. 0.04 951
Feb. 22, 2013