RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 16 LCD CONTROLLER/DRIVER (3) LCD clock control register (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and the number of time slices. LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LCDC0 to 00H. Figure 16-4. Format of LCD Clock Control Register Address: FFF42H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 LCDC0 0 LCDC6 LCDC5 LCDC4 0 LCDC2 LCDC1 LCDC0 LCDC6 LCDC5 LCDC4 LCD source clock (fLCD) selection R01UH0317EJ0004 Rev. 0.04 971 Feb. 22, 2013 fMAIN = 4MHz fMAIN = 8MHz 0 0 0 fXT 32.768kHz fMAIN = 20MHz fMAIN = 24MHz (fIH only) 0 0 1 fMAIN/2 5 125kHz 250kHz 625kHz 750kHz 0 1 0 fMAIN/2 6 62.5kHz 125kHz 312.5kHz 375kHz 0 1 1 fMAIN/2 7 31.25kHz 62.5kHz 156.25kHz 187.5kHz 1 0 0 fMAIN/2 8 15.625kHz 31.25kHz 78.125kHz 93.75kHz 1 0 1 fMAIN/2 9 7.81kHz 15.625kHz 39.06kHz 46.875kHz 1 1 0 fMAIN/2 1 0 1 1 1 fIL 15kHz (typ.) LCDC2 LCDC1 LCDC0 fLCD = 32.768kHz 7.81kHz 19.53kHz 23.43kHz LCD(LCDCL) selection fLCD = 31.25kHz fLCD = 46.875kHz fLCD = 15kHz 0 0 0 fLCD/2 4 2048Hz 1953.13Hz 2929.69Hz 937.5Hz 0 0 1 fLCD/2 5 1024Hz 976.56Hz 1464.84Hz 468.75Hz 0 1 0 fLCD/2 6 512Hz 488.28Hz 732.42Hz 234.38Hz 0 1 1 fLCD/2 7 256Hz 244.14Hz 366.21Hz 117.19Hz 1 0 0 fLCD/2 8 128Hz 122.07Hz 183.1Hz 58.59Hz 1 0 1 fLCD/2 9 64Hz 61.04Hz 91.55Hz 29.29Hz Other than above Setting prohibited (same as “000” setting) Caution Bits 3 and 7 must be set to 0. Remarks 1. fXT: XT1 clock oscillation frequency 2. fIL: Low-speed on-chip oscillator clock frequency
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 16 LCD CONTROLLER/DRIVER LCD frame frequency (Hz) example : Duty LCDCL = 64Hz LCDCL = 128Hz (T = 15.6ms) (T = 7.8ms) LCDCL = 256Hz (T = 3.9ms) LCDCL = 122.07Hz (T = 8.192ms) LCDCL = 244.14Hz (T = 4.096ms) LCDCL = 234.38Hz (T = 4.27ms) 1/3 21 43 85 40 81 78 1/4 16 32 64 30 61 58 Static 64 128 256 122 244 234 Remark Frame period TF = 3 ×T when 1/3 duty mode TF = 4 ×T when 1/4 duty mode TF = T when static mode R01UH0317EJ0004 Rev. 0.04 972 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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