RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER Figure 19-10. Example of Setting for UART Consecutive Reception + ACK Transmission Start DEN0 = 1 DSA0 = 4AH DRA0 = FE00H DBC0 = 0040H DMC0 = 0BH Setting for UART reception DST0 = 1 User program processing INTLR0 occurs. INTDMA0 occurs. DST0 = 0 DEN0 = 0 Note RETI End INTLR0 interrupt routine STG0 = 1 DMA0 transfer P10 = 1 P10 = 0 R01UH0317EJ0004 Rev. 0.04 1043 Feb. 22, 2013 RETI Hardware operation Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details, refer to 19.5.5 Forced termination by software). Remark This is an example where a software trigger is used as a DMA start source. If ACK is not transmitted and if only data is consecutively received from UART, the UART reception end interrupt (INTLR0) can be used to start DMA for data reception.
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER 19.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1. The DMA transfer for a transfer trigger that occurred while DMA transfer was held pending is executed after the pending status is canceled. However, because only one transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the pending status, only one DMA transfer is executed after the pending status is canceled. To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock width increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by setting the DWAITn bit to 1. After setting the DWAITn bit to 1, it takes two clocks until a DMA transfer is held pending. Figure 19-11. Example of Setting for Holding DMA Transfer Pending by DWAITn Bit Starting DMA transfer Main program DWAITn = 1 Wait for 2 clocks P10 = 1 Wait for 9 clocks P10 = 0 DWAITn = 0 Caution When DMA transfer is held pending while using two or more DMA channels, be sure to held the DMA transfer pending for all channels (by setting DWAIT0, DWAIT1, DWAIT2, and DWAIT3 to 1). If the DMA transfer of one channel is executed while that of the other channel is held pending, DMA transfer might not be held pending for the latter channel. Remarks 1. n: DMA channel number (n = 0 to 3) 2. 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0317EJ0004 Rev. 0.04 1044 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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