RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) When the 2BF reception trigger bit (UFnBRT) is set, a successful BF reception wait state (UFnBRF = 1) is entered, the LRxDn input level is monitored, and start bit detection is performed. When the falling edge of the LRxDn input level is detected, the BF length is measured by counting up the internal counter until a rising edge is detected. If the BF length is at least 11 bits when a rising edge has been detected, BF reception is judged as being normal, the BF reception flag (UFnBRF) is automatically cleared, and BF reception ends. When ending BF reception, a successful BF reception flag (UFnBSF) is set at the same time as a status interrupt request signal (INTLSn) is generated when in BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B). Detection of overrun, parity, and framing (UFnOVE, UFnPE, UFnFE) errors is controlled. Moreover, data transfer from the receive shift register to the receive data register (UFnRX) is not performed. BF reception is judged as being abnormal if the BF width is less than 11 bits. In that case, reception ends without generating a reception complete interrupt request signal (INTLRn) or a status interrupt request signal (INTLSn) and operation is returned to a successful BF reception wait state (UFnBRF = 1) again. At that time, the BF reception flag (UFnBRF) is not cleared. When performing a transmission for which a data consistency check is enabled (UFnDCS = 1), a data consistency error flag (UFnDCE) is set and a status interrupt request signal (INTLSn) is output when a mismatch between the transmit data and receive data is detected, regardless of whether BF reception is performed successfully or fails. At that time, INTLRn is not output. When in BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B), LIN-UART can detect a new BF reception even during data communication. See 13.5.9 (2) BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B) for details. Remark n = 0, 1 R01UH0317EJ0004 Rev. 0.04 733 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) UFnBRF flag INTLSn signal UFnBSF flag UFnBRF flag INTLSn signal UFnBSF flag Figure 13-35. BF Reception Timing Example • Normal BF reception: A high level is detected after the BF length has exceeded 11 bits. Set the UFnBRT bit. 1 2 3 4 5 6 7 8 9 10 11 Set the UFnBRT bit. R01UH0317EJ0004 Rev. 0.04 734 Feb. 22, 2013 11 bits • BF reception error: A high level is detected when the BF length is less than 11 bits. “0” “0” 1 2 3 4 5 6 7 8 9 10 11 Caution The UFnBRF bit is reset by setting the UFnBRT bit to “1” and cleared upon normal BF reception. Remark n = 0, 1 11 bits
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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