RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
(3) Operation of TOmn pin in combination operation mode (TOMmn = 1)
(a) When TOLmn setting has been changed during timer operation
When the TOLmn setting has been changed during timer operation, the setting becomes valid at the
generation timing of TOmn change condition. Rewriting TOLmn does not change the output level of TOmn.
The following figure shows the operation when the value of TOLmn has been changed during timer operation
(TOMmn = 1).
Figure 6-44. Operation When TOLmn Has Been Changed During Timer Operation
Internal set signal
Internal reset signal
TOLmn
TOmn pin
TOmn does not change
Set/reset signals are inverted
Remarks 1. Set: The output signal of TOmn pin changes from inactive level to active level.
Reset: The output signal of TOmn pin changes from active level to inactive level.
2. m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-40 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0
Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0
R01UH0317EJ0004 Rev. 0.04 396
Feb. 22, 2013