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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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<br />

Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 3 CPU ARCHITECTURE<br />

FFFFFH<br />

FFF20H<br />

FFF1FH<br />

FFF00H<br />

FFEFFH<br />

FFEE0H<br />

FFEDFH<br />

FFE20H<br />

FFE1FH<br />

FEF00H<br />

FEEFFH<br />

F3000H<br />

F2FFFH<br />

F1000H<br />

F0FFFH<br />

F0800H<br />

F07FFH<br />

F0000H<br />

EFFFFH<br />

20000H<br />

1FFFFH<br />

00000H<br />

Figure 3-13. Correspondence Between Data Memory and Addressing<br />

(R5F10DMG, R5F10DPG)<br />

Special function register (SFR)<br />

256 bytes<br />

General-purpose register<br />

32 bytes<br />

RAM Note<br />

8 KB<br />

Mirror<br />

43.75 KB<br />

Data flash memory<br />

8 KB<br />

Reserved<br />

Special function register (2nd SFR)<br />

2 KB<br />

Reserved<br />

Code flash memory<br />

128 KB<br />

SFR addressing<br />

Register addressing<br />

Short direct<br />

addressing<br />

Direct addressing<br />

Register indirect addressing<br />

Based addressing<br />

Based indexed addressing<br />

Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash<br />

function.<br />

Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS<br />

= 0), be sure to initialize the used RAM area + 10 bytes.<br />

R01UH0317EJ0004 Rev. 0.04 91<br />

Feb. 22, 2013

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