RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER (26) Port mode registers 0, 6, 7, 13 (PM0, PM6, PM7, PM13) The PM0, PM6, PM7 and PM13 registers are used to set ports 0, 6, 7 and 13 to input or output in 1-bit units. When using the P00/CTxD0 or P71/CTxD0 pins for serial data output, clear the PM00 or PM71 bits to “0”, and set the output latches of P00 or P71 to “1”. When using the P62/CTxD1 or P134/CTxD1 pins for serial data output, clear the PM62 or PM134 bits to “0”, and set the output latches of P62 or P134 to “1”. When using the P01/CRxD0 or P70/CRxD0 pins for serial data input, set the PM01 or PM70 bits to “1”. At this time, the output latches of P01 or P70 may be “0” or “1”. When using the P63/CRxD1 or P135/CRxD1 pins for serial data input, set the PM63 or PM135 bits to “1”. At this time, the output latches of P63 or P135 may be “0” or “1”. The PM1, PM6, PM7, PM13 registers can be set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Caution The serial data output and serial data input are provided at two ports per channel. Select either port by using the corresponding register. Remark The pins mounted depend on the product. See 1.4 Pin Configuration and 2.1 Pin Function List. Figure 14-52. Format of Port Mode Registers 0, 6, 7, 13 (PM0, PM6, PM7, PM13) Address: FFF20H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FFF26H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM6 1 PM66 PM65 PM64 PM63 PM62 PM61 PM60 Address: FFF27H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM7 1 1 PM75 PM74 PM73 PM72 PM71 PM70 Address: FFF2DH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM13 1 PM136 PM135 PM134 PM133 PM132 PM131 0 PMmn PMmn pin I/O mode selection (m = 1, 6, 7, 13 ; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0317EJ0004 Rev. 0.04 881 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.8 CAN Controller Initialization This chapter is explaining the case of CAN channel 0 for register symbol to the example. In the case of CAN channel 1, please transpose 0 to 1, and read it (ex.: C0GMCS C1GMCS). 14.8.1 Initialization of CAN module Before the CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the C0GMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled. The CAN module is enabled by setting the GOM bit of the C0GMCTRL register. For the procedure of initializing the CAN module, refer to 14.16 Operation Of CAN Controller. 14.8.2 Initialization of message buffer After the CAN module is enabled, the message buffers contain undefined values. A minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the CAN module from the initialization mode to one of the operation modes. - Clear the RDY, TRQ, and DN bits of the C0MCTRLm register to 0. - Clear the MA0 bit of the C0MCONFm register to 0. Remark m = 0 to 15 14.8.3 Redefinition of message buffer Redefining a message buffer means changing the ID and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) To redefine message buffer in initialization mode Place the CAN module in the initialization mode once and then change the ID and control information of the message buffer in the initialization mode. After changing the ID and control information, set the CAN module in an operation mode. (2) To redefine message buffer during reception Perform redefinition as shown in Figure 14-66. (3) To redefine message buffer during transmission To rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (refer to 14.10.4 (1) Transmission abort process except for in normal operation mode with automatic block transmission (ABT) and 14.10.4 (2) Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT). Confirm that transmission has been aborted or completed, and then redefine the message buffer. After redefining the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. R01UH0317EJ0004 Rev. 0.04 882 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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34.2 64-pin products 1276 R5F10CLDx
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