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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

(b) Write<br />

Figure 14-44. Format of CAN Module Transmit History List Register (C0TGPT, C1TGPT) (2/2)<br />

Clear TOVF Setting of TOVF Bit<br />

0 TOVF bit is not changed.<br />

1 TOVF bit is cleared to 0.<br />

(19) CAN module time stamp register (C0TS, C1TS)<br />

The C0TS, C1TS register is used to control the time stamp function.<br />

(a) Read<br />

(b) Write<br />

Figure 14-45. Format of CAN Module Time Stamp Register (C0TS, C1TS) (1/2)<br />

Address: F05F6H (C0TS), F03A6H (C1TS) After reset: 0000H R/W<br />

C0TS,<br />

C1TS<br />

C0TS,<br />

C1TS<br />

(a) Read<br />

15 14 13 12 11 10 9 8<br />

0 0 0 0 0 0 0 0<br />

7 6 5 4 3 2 1 0<br />

0 0 0 0 0 TSLOCK TSSEL TSEN<br />

15 14 13 12 11 10 9 8<br />

0 0 0 0 0 Set<br />

TSLOCK<br />

Set<br />

TSSEL<br />

Set<br />

TSEN<br />

7 6 5 4 3 2 1 0<br />

0 0 0 0 0 Clear<br />

TSLOCK<br />

Clear<br />

TSSEL<br />

Clear<br />

TSEN<br />

Remark The lock function of the time stamp function must not be used when the CAN module<br />

is in the normal operation mode with ABT.<br />

TSLOCK Time Stamp Lock Function Enable Bit<br />

0 Time stamp lock function stopped.<br />

The TSOUT signal is toggled each time the selected time stamp capture event occurs.<br />

1 Time stamp lock function enabled.<br />

The TSOUT signal is toggled each time the selected time stamp capture event occurs.<br />

However, the TSOUT output signal is locked when a data frame has been correctly<br />

received to message buffer 0 Note .<br />

Note The TSEN bit is automatically cleared to 0.<br />

R01UH0317EJ0004 Rev. 0.04 870<br />

Feb. 22, 2013

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