RL78/D1A User's Manual: Hardware - Renesas

2.2.3 P20 to P27 (port2) ............................................................................................................................ 41
2.2.4 P30 to P37 (port3) ............................................................................................................................ 42
2.2.5 P40 (port4) ....................................................................................................................................... 43
2.2.6 P50 to P57 (port5) ............................................................................................................................ 43
2.2.7 P60 to P66 (port6) ............................................................................................................................ 44
2.2.8 P70 to P75 (port7) ............................................................................................................................ 45
2.2.9 P80 to P87 (port8) ............................................................................................................................ 47
2.2.10 P90 to P97 (port9) .......................................................................................................................... 47
2.2.11 P121 to P124 (port12) .................................................................................................................... 49
2.2.12 P130 to P137 (port13) .................................................................................................................... 49
2.2.13 P140 (port14) ................................................................................................................................. 51
2.2.14 P150 (port15) ................................................................................................................................. 51
2.2.15 COM0 to COM3.............................................................................................................................. 51
2.2.16 VDD, EVDD0, EVDD1, SMVDD0, SMVDD1, VSS, EVSS0, EVSS1, SMVSS0, SMVSS1 ............. 52
2.2.17 RESET ........................................................................................................................................... 52
2.2.18 REGC............................................................................................................................................. 52
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................................. 53
CHAPTER 3 CPU ARCHITECTURE ....................................................................................................... 68
3.1 Memory Space .................................................................................................................................... 68
3.1.1 Internal program memory space....................................................................................................... 79
3.1.2 Mirror area........................................................................................................................................ 83
3.1.3 Internal data memory space............................................................................................................. 85
3.1.4 Special function register (SFR) area ................................................................................................ 86
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 86
3.1.6 Data memory addressing ................................................................................................................. 87
3.2 Processor Registers........................................................................................................................... 93
3.2.1 Control registers............................................................................................................................... 93
3.2.2 General-purpose registers................................................................................................................ 95
3.2.3 ES and CS registers......................................................................................................................... 97
3.2.4 Special function registers (SFRs)..................................................................................................... 98
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 104
3.3 Instruction Address Addressing..................................................................................................... 131
3.3.1 Relative addressing........................................................................................................................ 131
3.3.2 Immediate addressing .................................................................................................................... 131
3.3.3 Table indirect addressing ............................................................................................................... 132
3.3.4 Register direct addressing.............................................................................................................. 133
3.4 Addressing for Processing Data Addresses ................................................................................. 134
3.4.1 Implied addressing ......................................................................................................................... 134
3.4.2 Register addressing ....................................................................................................................... 134
3.4.3 Direct addressing ........................................................................................................................... 135
Index-2