RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 19 DMA CONTROLLER
19.4 Operation of DMA Controller
19.4.1 Operation procedure
The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the
DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.
Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to
DMA SFR address register n (DSAn), DMA RAM address register n (DRAn), DMA byte count register n (DBCn),
and DMA mode control register n (DMCn).
The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
instruction.
When a software trigger (STGn) or a start source trigger specified by the IFCn3 to IFCn0 bits is input, a DMA
transfer is started.
Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is
automatically terminated by occurrence of an interrupt (INTDMAn).
Stop the operation of the DMA controller by clearing the DENn bit to 0 when the DMA controller is not used.
Remark n: DMA channel number (n = 0 to 3)
Figure 19-7. Operation Procedure
DENn = 1
Setting DSAn, DRAn, DBCn, and DMCn
DSTn = 1
DMA trigger = 1?
Yes
Transmitting DMA request
Receiving DMA acknowledge
DMA transfer
DRAn = DRAn + 1 (or + 2)
DBCn = DBCn 1
DBCn = 0000H ?
Yes
DSTn = 0
INTDMAn = 1
DENn = 0
R01UH0317EJ0004 Rev. 0.04 1036
Feb. 22, 2013
No
No
Set by software program
Operation by DMA
controller (hardware)
Set by software program