RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (3) Transmission interrupt request signal (INTLTn) When a transmission interrupt request is set to output upon starting a transmission (UFnITS = 0), a transmission interrupt request signal is generated when transmission from the UFnTX register to the transmit shift register has been completed. When a transmission interrupt request is set to output upon completion of a transmission (UFnITS = 1), a transmission interrupt request signal is generated when transmitting a stop bit has been completed. Remark n = 0, 1 R01UH0317EJ0004 Rev. 0.04 717 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.5 Operation 13.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 13-20, one data frame of transmit/receive data consists of a start bit, character bits, an expansion bit, a parity bit, and stop bits. Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UFnCTL0 register. Moreover, the UFnTDL bit and UFnRDL bit of the UFnOPT0 register are used to control UART output/inverted output for the LTxDn pin and UART input/inverted input for the LRxDn pin, respectively. Remark n = 0, 1 Start bit.................... 1 bit Character bits.......... 7 bits/8 bits Expansion bit .......... 1 bit Parity bit.................. Even parity/odd parity/0 parity/no parity Stop bit.................... 1 bit/2 bits Figure 13-21. Format of LIN-UART Transmit/Receive Data (1/2) (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H Start bit 1 data frame D0 D1 D2 D3 D4 D5 D6 D7 Parity bit (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H Start bit 1 data frame D7 D6 D5 D4 D3 D2 D1 D0 Parity bit (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, LTxDn inversion Start bit 1 data frame D7 D6 D5 D4 D3 D2 D1 D0 Parity bit (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H Start bit 1 data frame D0 D1 D2 D3 D4 D5 D6 Parity bit R01UH0317EJ0004 Rev. 0.04 718 Feb. 22, 2013 Stop bit Stop bit Stop bit Stop bit Stop bit
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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