RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR 24.5 Cautions for Voltage Detector (1) Checking reset source When a reset occurs, check the reset source by using the following method. Figure 24-9. Checking reset source Check reset source TRAP of RESF register = 1? No WDTRF of RESF register = 1? No RPERF of RESF register = 1? No IAWRF of RESF register = 1? No LVIRF of RESF register = 1? Yes Reset processing by voltage detector Note When instruction code FFH is executed. Yes Yes Yes Yes No Reset processing by illegal instruction execution Note Reset processing by watchdog timer Reset processing by RAM parity error Reset processing by illegal-memory access Power-on-reset/external reset generated Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0317EJ0004 Rev. 0.04 1131 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has been generated. In the same way, there is also some delay from the time LVD detection voltage (VLVD) supply voltage (VDD) until the time LVD reset has been released (see Figure 24-8). Figure 24-10. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released Supply voltage (V DD ) V LVD LVIF flag LVD reset signal : Detection delay (200 s (MAX.)) Minimum pulse width (TLW) 200 s R01UH0317EJ0004 Rev. 0.04 1132 Feb. 22, 2013 Time
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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RL78/D1A User’s Manual: Hardware
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