RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 25 SAFETY FUNCTIONS (1) Flash memory CRC control register (CRC0CTL) This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: F02F0H After reset: 00H R/W Figure 25-1. Format of Flash Memory CRC Control Register (CRC0CTL) Symbol 6 5 4 3 2 1 0 CRC0CTL CRC0EN 0 FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 CRC0EN Control of CRC ALU operation 0 Stop the operation. 1 Start the operation according to HALT instruction execution. FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 CRC operation range 0 0 0 0 0 0 0 to 3FFBH (16 K - 4 bytes) 0 0 0 0 0 1 0 to 7FFBH (32 K - 4 bytes) 0 0 0 0 1 0 0 to BFFBH (48 K - 4 bytes) 0 0 0 0 1 1 0 to FFFBH (64 K - 4 bytes) 0 0 0 1 0 0 0 to 13FFBH (80 K to 4 bytes) 0 0 0 1 0 1 0 to 17FFBH (96 K to 4 bytes) 0 0 0 1 1 0 0 to 1BFFBH (112 K to 4 bytes) 0 0 0 1 1 1 0 to 1FFFBH (128 K to 4 bytes) 0 0 1 0 0 0 0 to 23FFBH (144 K to 4 bytes) 0 0 1 0 0 1 0 to 27FFBH (160 K to 4 bytes) 0 0 1 0 1 0 0 to 2BFFBH (176 K to 4 bytes) 0 0 1 0 1 1 0 to 2FFFBH (192 K to 4 bytes) 0 0 1 1 0 0 0 to 33FFBH (208 K to 4 bytes) 0 0 1 1 0 1 0 to 37FFBH (224 K to 4 bytes) 0 0 1 1 1 0 0 to 3BFFBH (240 K to 4 bytes) 0 0 1 1 1 1 0 to 3FFFBH (256 K to 4 bytes) Other than the above Setting prohibited Remark Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash memory. Note that the operation range will thereby be reduced by 4 bytes. R01UH0317EJ0004 Rev. 0.04 1135 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 25 SAFETY FUNCTIONS (2) Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 25-2. Format of Flash Memory CRC Operation Result Register (PGCRCL) Address: F02F2H After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 PGCRCL PGCRC15 PGCRC14 PGCRC13 PGCRC12 PGCRC11 PGCRC10 PGCRC9 PGCRC8 Address: F02F1H After reset: 0000H R/W Symbol 7 6 5 4 3 2 1 0 PGCRCL PGCRC7 PGCRC6 PGCRC5 PGCRC4 PGCRC3 PGCRC2 PGCRC1 PGCRC0 PGCRC15 to 0 CRC operation results 0000H to FFFFH Store the CRC operation results. Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1. Figure 25-3 shows the flowchart of flash memory CRC operation function (high-speed CRC). R01UH0317EJ0004 Rev. 0.04 1136 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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