RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER (8) ZPD flag detection clock setting register (CMPCTL) The 8-bit CMPCTL register controls the clock for noise elimination. This register can be read/written in 8-bit or 1-bit units. This register is cleared by any reset. Figure 15-6. Format of ZPD Flag Detection Clock Setting Register (CMPCTL) Address: F015EH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CMPCTL 0 0 0 0 DBCL3 DBCL2 DBCL1 DBCL0 DBCL3 DBCL2 DBCL1 DBCL0 Selected clock 0 0 0 0 fCLK 0 0 0 1 fCLK/2 0 0 1 0 fCLK/2 2 0 0 1 1 fCLK/2 3 0 1 0 0 fCLK/2 4 0 1 0 1 fCLK/2 5 0 1 1 0 fCLK/2 6 0 1 1 1 fCLK/2 7 1 0 0 0 fCLK/2 8 1 0 0 1 fCLK/2 9 Other than above Setting prohibited (9) ZPD operational control register (ZPDEN) The 8-bit ZPDEN register controls ZPD operation. These registers can be read/written in 8-bit or 1-bit units. This register is cleared by any reset. Figure 15-7. Format of ZPD Operational Control Register (ZPDEN) Address: F015FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ZPDEN 0 0 0 0 ZPD4EN ZPD3EN ZPD2EN ZPD1EN ZPDkEN ZPDk comparator operation (k = 1 to 4) 0 Disables operation. 1 Enables operation. R01UH0317EJ0004 Rev. 0.04 957 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER (10) Peripheral enable registers 1 (PER1) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is stopped in order to reduce the power consumption and noise. When the Stepper Motor Controller/Driver is used, be sure to set bit 5 (MTRCEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 15-8. Format of Peripheral Enable Registers 1 (PER1) Address: F00F1H After reset: 00H R/W (Note: Bits 0 to 3 and 6 are Read Only) Symbol 7 6 5 4 3 2 1 0 PER1 ADCEN 0 MTRCEN SGEN 0 0 0 0 MTRCEN Control of stepper motor controller/driver clock supply 0 Stops input clock supply. SFR used by the stepper motor controller/driver cannot be written. The stepper motor controller/driver is in the reset status. 1 Supplies input clock. SFR used by stepper motor controller/driver can be read and written. R01UH0317EJ0004 Rev. 0.04 958 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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