RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1291 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F01F0 - - - - F01F2 - - - - F01F4 TE1 (Timer channel enable status register 1) - - R - - - - - - - - TE1L R R - R R R R R R R R TE1_7 TE1_6 TE1_5 TE1_4 TE1_3 TE1_2 TE1_1 TE1_0 R R R R R R R R TS1 (Timer channel start trigger register 1) - - E - - - - - - - - TS1L E E - E E E E E E E E TS1_7 TS1_6 TS1_5 TS1_4 TS1_3 TS1_2 TS1_1 TS1_0 E E E E E E E E TT1 (Timer channel stop trigger register 1) - - E - - - - - - - - TT1L E E - E E E E E E E E TT1_7 TT1_6 TT1_5 TT1_4 TT1_3 TT1_2 TT1_1 TT1_0 E E E E E E E E - - - - F01F6 TPS1 (Timer clock select register 1) - - E - - - - - - - - - - - - F01F8 - - - - F01FA - - - - F01FC - - - - F01FE TO1 (Timer output register 1) - - E - - - - - - - - TO1L - E - - - - - - - - - TOE1 (Timer output enable register 1) - - E - - - - - - - - TOE1L E E - E E E E E E E E TOE1_7 TOE1_6 TOE1_5 TOE1_4 TOE1_3 TOE1_2 TOE1_1 TOE1_0 E E E E E E E E TOL1 (Timer output level register 1) - - E - - - - - - - - TOL1L - E - - - - - - - - - TOM1 (Timer output mode register 1) - - E - - - - - - - - TOM1L - E - - - - - - - - - - - - - F0200 TCR20 (Timer counter register 20) - - R - - - - - - - - - - - - F0202 TCR21 (Timer counter register 21) - - R - - - - - - - - - - - - F0204 TCR22 (Timer counter register 22) - - R - - - - - - - - - - - - F0206 TCR23 (Timer counter register 23) - - R - - - - - - - - - - - - F0208 TCR24 (Timer counter register 24) - - R - - - - - - - - - - - - F020A TCR25 (Timer counter register 25) - - R - - - - - - - - - - - - F020C TCR26 (Timer counter register 26) - - R - - - - - - - - - - - - F020E TCR27 (Timer counter register 27) - - R - - - - - - - - - - - - F0210 TMR20 (Timer mode register 20) - - E - - - - - - - - - - - - F0212 TMR21 (Timer mode register 21) - - E - - - - - - - - - - - - F0214 TMR22 (Timer mode register 22) - - E - - - - - - - - - - - - F0216 TMR23 (Timer mode register 23) - - E - - - - - - - - 1291 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1292 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F0218 TMR24 (Timer mode register 24) - - E - - - - - - - - - - - - F021A TMR25 (Timer mode register 25) - - E - - - - - - - - - - - - F021C TMR26 (Timer mode register 26) - - E - - - - - - - - - - - - F021E TMR27 (Timer mode register 27) - - E - - - - - - - - - - - - F0220 - - - - F0222 - - - - F0224 - - - - F0226 - - - - F0228 - - - - F022A - - - - F022C - - - - F022E - - - - F0230 - - - - F0232 - - - - F0234 TSR20 (Timer status register 20) - - R - - - - - - - - TSR20L - R - - - - - - - - - TSR21 (Timer status register 21) - - R - - - - - - - - TSR21L - R - - - - - - - - - TSR22 (Timer status register 22) - - R - - - - - - - - TSR22L - R - - - - - - - - - TSR23 (Timer status register 23) - - R - - - - - - - - TSR23L - R - - - - - - - - - TSR24 (Timer status register 24) - - R - - - - - - - - TSR24L - R - - - - - - - - - TSR25 (Timer status register 25) - - R - - - - - - - - TSR25L - R - - - - - - - - - TSR26 (Timer status register 26) - - R - - - - - - - - TSR26L - R - - - - - - - - - TSR27 (Timer status register 27) - - R - - - - - - - - TSR27L - R - - - - - - - - - TE2 (Timer channel enable status register 2) - - R - - - - - - - - TE2L R R - R R R R R R R R TE2_7 TE2_6 TE2_5 TE2_4 TE2_3 TE2_2 TE2_1 TE2_0 R R R R R R R R TS2 (Timer channel start trigger register 2) - - E - - - - - - - - TS2L E E - E E E E E E E E TS2_7 TS2_6 TS2_5 TS2_4 TS2_3 TS2_2 TS2_1 TS2_0 E E E E E E E E TT2 (Timer channel stop trigger register 2) - - E - - - - - - - - TT2L E E - E E E E E E E E TT2_7 TT2_6 TT2_5 TT2_4 TT2_3 TT2_2 TT2_1 TT2_0 E E E E E E E E - - - - F0236 TPS2 (Timer clock select register 2) - - E - - - - - - - - 1292 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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RL78/D1A User's Manual: Hardware - Renesas

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