RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
(3) Timer mode register mn (TMRmn)
TMRmn sets an operation mode of channel n. It is used to select an operation clock (fMCK), a count clock, whether
the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the timer input,
and an operation mode (interval, capture, event counter, one-count, or capture & one-count).
Rewriting TMRmn is prohibited when the register is in operation (when TEm = 1). However, bits 7 and 6 (CISmn1,
CISmn0) can be rewritten even while the register is operating with some functions (when TEm = 1) (for details, see
6.7 Operation of Timer Array Unit as Independent Channel and 6.8 Operation of Plural Channels of Timer
Array Unit).
TMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/3)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H R/W
F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17),
F0210H, F0211H (TMR20) to F021EH, F021FH (TMR27)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn CKS
mn1
CKS
mn1
CKS
mn0
CKS
mn0
0 CCS
mn0
MAST
ERmn
STS
mn2
STS
mn1
STS
mn0
0 0 Operation clock CKm0 set byTPSm register
0 1 Operation clock CKm1 set by TPSm register
1 0 Operation clock CKm2 set by TPSm register
1 1 Operation clock CKm3 set by TPSm register
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Feb. 22, 2013
CIS
mn1
CIS
mn0
0 0 MD
mn3
Selection of operation clock (fMCK) of channel n
Operation clock (fMCK) is used by the edge detector. A count clock (fTCLK) is generated depending on the setting of
the CCSmn bit.
CCS
mn0
0 Operation clock (fMCK) specified by CKSmn bit
1 Valid edge of input signal input from TImn pin
Selection of count clock (fTCLK) of channel n
Count clock (fTCLK) is used for the timer counter, output controller, and interrupt controller.
Cautions 1. Be sure to clear bits 13, 5, and 4 to “0”.
2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is
changed (by changing the value of the system clock control register (CKC)), even if the
operating clock specified by using the CKSmn bit (fMCK), or the valid edge of the signal
input from the TImn pin is selected as the count clock (fTCLK).
Remark m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
MD
mn2
MD
mn1
MD
mn0