RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER BOFF bit in C0INFO, C1INFO register OPMODE[2:0] in C0CTRL, C1CTRL register (user writings) OPMODE[2:0] in C0CTRL, C1CTRL register (user readings) TEC[7:0] in C0ERC, C1ERC register REPS, REC[6:0] in C0ERC, C1ERC register Figure 14-17. Recovery Operation from Bus-off State through Normal Recovery Sequence »error-passive« TEC > FFH 80H ≤ TEC[7:0] ≤ FFH ≠ 00H 00H ≠ 00H ≠ 00H »bus-off« »bus-off-recovery-sequence« »error-active« FFH < TEC [7:0] 80H ≤ REPS, REC[6:0] ≤ FFH 00H ≠ 00H R01UH0317EJ0004 Rev. 0.04 803 Feb. 22, 2013 00H Undefined 00H ≤ TEC[7:0] < 80H 00H ≤ REPS, REC[6:0] < 80H (b) Forced recovery operation that skips bus-off recovery sequence The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. Here is the procedure. First, the CAN module requests to enter the initialization mode. For the operation and points to be noted at this time, refer to (a) Recovery operation from bus-off state through normal recovery sequence. Next, the module requests to enter an operation mode. At the same time, the CCERC bit of the C0CTRL, C1CTRL register must be set to 1. As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the module immediately enters the operation mode. In this case, the module is connected to the CAN bus after it has monitored 11 consecutive recessive-level bits. For details, refer to the processing in Figure 14-82. Caution This function is not defined by the CAN protocol ISO 11898. When using this function, thoroughly evaluate its effect on the network system. (6) Initializing CAN module error counter register (C0ERC, C1ERC) in initialization mode If it is necessary to initialize the CAN module error counter register (C0ERC, C1ERC) and CAN module information register (C0INFO, C1INFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the C0CTRL, C1CTRL register in the initialization mode. When initialization has been completed, the CCERC bit is automatically cleared to 0. Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1 in a CAN operation mode, the C0ERC, C1ERC and C0INFO, C1INFO registers are not initialized. 2. The CCERC bit can be set at the same time as the request to enter a CAN operation mode.
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a CAN protocol layer basic clock (fTQ) derived from the CAN module system clock (fCANMOD), and divided by 1 to 256 (refer to 14.6 (12) CAN Bit Rate Prescaler Register (C0BRP, C1BRP)). (2) Data bit time (8-25 time quanta) One data bit time is defined as shown in Figure 14-18. The CAN controller sets time segment 1, time segment 2, and reSynchronization Jump Width (SJW) as the parameter of data bit time, as shown in Figure 14-18. Time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN protocol specification. Time segment 2 is equivalent to phase segment 2. Figure 14-18. Segment Setting Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Time segment 1(TSEG1) Time segment 2 (TSEG2) Sample point (SPT) Segment Name Settable Range Notes on Setting to Confirm to CAN Specification Time Segment 1 (TSEG1) 2TQ-16TQ — Time Segment 2 (TSEG2) 1TQ-8TQ IPT of the CAN controller is 0TQ. To conform to the CAN protocol specification, therefore, a length less or equal to phase segment 1 must be set here. This means that the length of time segment 1 minus 1TQ is the settable upper limit of time segment 2. Resynchronization jump width(SJW) Remark IPT : Information Processing Time TQ : Time Quanta 1TQ-4TQ The length of time segment 1 minus 1TQ or 4 TQ, whichever is smaller. R01UH0317EJ0004 Rev. 0.04 804 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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