RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT
(10) Serial channel stop register m (STm)
STm is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0. Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
STm can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of STm can be set with an 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears this register to 0000H.
Figure 12-15. Format of Serial Channel Stop Register m (STm)
Address: F0114H, F0115H (ST0), F0144H, F0145H (ST1), After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STm
1
STm
n
0 No trigger operation
Operation stop trigger of channel n
1 Clears SEmn to 0 and stops the communication operation.
(Stops with the values of the control register and shift register, and the statuses of the serial clock I/O pin,
serial data output pin, and the PEF and OVF error flags retained Note .)
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Caution Be sure to clear bits 15 to 2 of STm to “0”.
Remarks 1. When the STm register is read, 0000H is always read.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
R01UH0317EJ0004 Rev. 0.04 579
Feb. 22, 2013
STm
0