RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (13) LIN-UARTn receive data register (UFnRX) The UFnRX register is a 16-bit register that is used to store receive data. Receive data of a character length specified by the UFnCL bit after reception completion will be stored into the UFnRX register when not in automatic baud rate mode (UFnMD1, UFnMD0 = 00B/10B) and when UFnEBE is “0”. When UFnEBE = UFnCL = 1, receive data of 9-bit length will be stored. This register is read-only, in 16-bit units. When the UFnRX register is read in 8-bit units, it can be accessed as the UFnRX register. Reset input sets this register to 0000H. Figure 13-13. Format of LIN-UARTn Receive Data Register (UFnRX) Address: FFF4AH, FFF4BH (UF0RX), FFF4EH, FFF4FH (UF1RX) After reset: 0000H R 15 14 13 12 11 10 9 8 UFnRX 0 0 0 0 0 0 0 UFnRX8 (n = 0, 1) 7 6 5 4 3 2 1 0 UFnRX7 UFnRX6 UFnRX5 UFnRX4 UFnRX3 UFnRX2 UFnRX1 UFnRX0 When the data length is specified as 7 bits (UFnCL bit = 0): During LSB-first reception, receive data is transferred to bits 6 to 0 of the UFnRX register and the MSB always becomes “0”. During MSB-first reception, receive data is transferred to bits 7 to 1 of the UFnRX register and the LSB always becomes “0”. When an overrun error (UFnOVE = 1) has occurred, the receive data at that time will not be transferred to the UFnRX register. Caution “0” is written to the UFnRX8 bit of UFnRX register when writing data to the UFnRXB register. Remark The UFnRX8 bit is an expansion bit when expansion bits are enabled (UFnEBE = UFnCL = 1). R01UH0317EJ0004 Rev. 0.04 707 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (14) LIN-UARTn 8-bit receive data register (UFnRXB) The UFnRXB register is an 8-bit register that is used to store receive data. Receive data of a character length specified by the UFnCL bit after reception completion will be stored into the UFnRX register when not in automatic baud rate mode (UFnMD1, UFnMD0 = 00B/10B) and when UFnEBE is “0”. This register is read-only, in 8-bit units. Reset input sets this register to 00H. Figure 13-14. Format of LIN-UARTn 8-bit Receive Data Register (UFnRXB) Address: FFF4AH (UF0RXB), FFF4EH (UF1RXB) After reset: 00H R 7 6 5 4 3 2 1 0 UFnRXB UFnRX7 UFnRX6 UFnRX5 UFnRX4 UFnRX3 UFnRX2 UFnRX1 UFnRX0 (n = 0, 1) When the data length is specified as 7 bits (UFnCL bit = 0): During LSB-first reception, receive data is transferred to bits 6 to 0 of the UFnRX register and the MSB always becomes “0”. During MSB-first reception, receive data is transferred to bits 7 to 1 of the UFnRX register and the LSB always becomes “0”. When an overrun error (UFnOVE = 1) has occurred, the receive data at that time will not be transferred to the UFnRX register. R01UH0317EJ0004 Rev. 0.04 708 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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