RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR 17.2 Sound Generator Registers The Sound Generator is controlled by means of the following registers: Table 17-1. Sound Generator Registers Overview Register name Shortcut Address Control register SG0CTL F0287H Frequency register SG0FL SG0FL F0280H Frequency register SG0FH SG0FH F0282H Amplitude register SG0PWM F0284H Duration factor register SG0SDF F0286H Interrupt threshold register SG0ITH F0288H Sound generator and PCL pin select register SGSEL FFF3FH (1) Peripheral enable register (PER1) and peripheral clock select register (PCKSEL) Peripheral enable register (PER1) Address: F00F1H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PER1 ADCEN 0 MTRCEN SGEN 0 0 0 0 Peripheral clock select register (PCKSEL) Address: F00F2H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PCKSEL 0 CAN SG clock source selection MCKE1 CAN MCK1 CAN MCKE0 R01UH0317EJ0004 Rev. 0.04 1001 Feb. 22, 2013 CAN MCK0 SGEN SGCLKSEL Selection of operation clock 0 0 SGCLK Bus clock supply 0 X Clock supply stopped Clock supply stopped (SFR write is impossible) 1 0 FCLK is supplied FCLK is supplied (SFR R/W is possible) 1 1 FCLK/2 is supplied FCLK is supplied (SFR R/W is possible) SEL
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR (2) Control register (SG0CTL) The 8-bit SG0CTL register controls the operation of the Sound Generator. This register can be read/written in 8-bit or 1-bit units. This register is cleared by any reset. Address: F0287H After reset: 00H R/W Figure 17-3. Format of Control Register (SG0CTL) Symbol 7 6 5 4 3 2 1 0 SG0CTL 0 0 0 SG0PWR 0 0 SG0OS SG0ALDS SG0PWR Power save mode selection 0 Clock input switched off (the Sound Generator is disabled and does not operate). 1 Clock input switched on (the Sound Generator is enabled and ready to use). SG0OS SG0 output mode selection 0 Selects frequency output at SGO/SGOF. 1 Selects frequency and amplitude mixed output at SGO/SGOF. SG0ALDS Automatic logarithmic decrement of amplitude 0 Automatic logarithmic decrement deactivated. 1 Automatic logarithmic decrement activated. Caution Change the contents of this register only when the sound is stopped (register SG0PWM cleared). R01UH0317EJ0004 Rev. 0.04 1002 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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