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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

Figure 14-66 shows the processing for a receive message buffer (MT [2:0] bits of C0MCONFm register = 001B to<br />

101B).<br />

Figure 14-66. Message Buffer Redefinition<br />

No<br />

START<br />

Clear VALID bit<br />

RDY = 1?<br />

Yes<br />

Clear RDY bit<br />

RDY = 0?<br />

RSTAT = 0 or<br />

Note 1<br />

VALID = 1?<br />

Set<br />

message buffers<br />

Set RDY bit<br />

END<br />

R01UH0317EJ0004 Rev. 0.04 922<br />

Feb. 22, 2013<br />

Yes<br />

Yes<br />

Note 2<br />

Wait for 4 CAN data bits<br />

Notes 1. Confirm that a message is being received because RDY bit must be set after a message is completely<br />

received.<br />

2. Avoid message buffer redefinition during store operation of message reception by waiting additional 4<br />

CAN data bits.<br />

No<br />

No

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