RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT
(7) Serial flag clear trigger register mn (SIRmn)
SIRmn is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because SIRmn is a trigger register, it is cleared immediately
when the corresponding bit of SSRmn is cleared.
SIRmn can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SIRmn can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears this register to 0000H.
Figure 12-12. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0104H, F0105H (SIR00), F0106H, F0107H (SIR01), After reset: 0000H R/W
F0134H, F0135H (SIR10), F0136H, F0137H (SIR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEC
Tmn
OVC
Tmn
0 No trigger operation
1 Clears the OVFmn bit of the SSRmn register to 0.
Clear trigger of overrun error flag of channel n
PECT11 Clear trigger of parity error of SCL11
0 No trigger operation
1 Clears PEF11 bit of SSR11 register to 0.
Cautions 1. Be sure to clear bits 15 to 2 of SIRmn to “0”.
2. Only the error flag set to the SSRn register is cleared by using the SIRmn register. When a
clear operation is performed for an error flag that is not set and when a new error is detected
between reading the error flag and the clear operation, the error flag may be erased.
Remarks 1. When the SIRmn register is read, 0000H is always read.
2. When writing “1” to a clear trigger and setting (1) the corresponding error flag occur simultaneously,
setting the error flag takes precedence.
3. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
R01UH0317EJ0004 Rev. 0.04 576
Feb. 22, 2013
OVC
Tmn