RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
14.6 Bit Set/Clear Function
The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface.
An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation,
read/modify/write, or direct writing of target values.
CAN global control register (C0GMCTRL, C1GMCTRL)
CAN global automatic block transmission control register (C0GMABT, C1GMABT)
CAN module control register (C0CTRL, C1CTRL)
CAN module interrupt enable register (C0IE, C1IE)
CAN module interrupt status register (C0INTS, C1INTS)
CAN module receive history list register (C0RGPT, C1RGPT)
CAN module transmit history list register (C0TGPT, C1TGPT)
CAN module time stamp register (C0TS, C1TS)
CAN message control register (C0MCTRLm, C1MCTRLm)
Remark m = 0 to 15
All the 16 bits in the above registers can be read via the usual method. Use the procedure described in figure 14-23
below to set or clear the lower 8 bits in these registers.
Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the
16-bit data after a write operation in Figure 14-24). Figure 14-23 shows how the values of set bits or clear bits relate to
set/clear/no change operations in the corresponding register.
Register’s current values
Write values
Register’s value after
write operations
Figure 14-23. Example of Bit Setting/Clearing Operations
0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1
0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0
set 0 0 0 0 1 0 1 1
clear 1 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
R01UH0317EJ0004 Rev. 0.04 841
Feb. 22, 2013
Bit status
Clear
Clear
No change
Clear
No change
No change
Set
Set