RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(4) LIN-UARTn option register 0 (UFnOPT0)
The UFnOPT0 register is an 8-bit register that controls serial communication operation of LIN-UARTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
Figure 13-4. Format of LIN-UARTn Option Register 0 (UFnOPT0) (1/3)
Address: F0241H (UF0OPT0), F0261H (UF1OPT0) After reset: 14H R/W
4 3 2 1 0
UFnOPT0
(n = 0, 1)
UFnBRF UFnBRT UFnBTT UFnBLS2 UFnBLS1 UFnBLS0 UFnTDL UFnRDL
UFnBRF BF reception flag
0 When the UFnCTL0.UFnRXE = 0 is set. Also upon normal end of BF reception.
1 While waiting for successful BF reception (when the UFnBRT bit is set)
BF (Break Field) reception is judged during LIN communication.
The UFnBRF bit retains “1” when a BF reception error occurs, and is cleared to “0” when BF
reception is started again and ends normally. It cannot be cleared by instruction.
The UFnBRF bit is read-only.
Caution When the UFnBRF bit is 1, whether BF reception has ended normally can be
judged by checking whether the low-level period is at least 11 bits, when a high
level, including noise, is input to the receive input data even for a moment. If the
low-level period is at least 11 bits, BF reception is judged to be performed
successfully.
When in BF reception enable mode during communication (UFnMD1, UFnMD0 =
10B), whether BF reception has ended normally when a status interrupt has been
detected after the BF reception trigger bit was set can be judged by checking that
the UFnBRF flag is “0” or the successful BF reception flag (UFnBSF) is “1” after a
reception complete interrupt or a status interrupt has been detected.
In either case, operation is performed as a normal UART reception from the next
reception after BF reception has been performed successfully.
UFnBRT BF reception trigger
0
1 BF reception trigger
This is the BF reception trigger bit during LIN communication, and when read, “0” is always read.
For BF reception, set (1) the UFnBRT bit to enable BF reception.
Set the UFnBRT bit after having set UFnCTL0.UFnRXE to “1”.
The status flag will not be updated, an interrupt request signal will not be generated, and data will
not be stored.
This bit can only be set again when the UFnBRF bit is 0.
When BF reception is enabled during communication, BF reception is detected as the low-level
period between when the UFnBRT bit is set and when the rising edge of the reception input data
is detected. Therefore, a BF will be detected even if the UFnBRT bit is set during BF reception.
Cautions 1. To release a BF reception enable state without receiving a BF, UFnRXE must be
cleared to 0.
2. Transmitting data while UFnDCS and UFnBRF are “1” is prohibited. BF
transmission, however, can be performed.
3. Setting the UFnBRT bit in automatic baud rate mode (UFnMD1, UFnMD0 = 11B)
is prohibited.
R01UH0317EJ0004 Rev. 0.04 688
Feb. 22, 2013