RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). - The phase error of the edge is given by the relative position of the detected edge and sync segment. 0: If the edge is within the sync segment Positive: If the edge is before the sample point (phase error) Negative: If the edge is after the sample point (phase error) If phase error is positive: Phase segment 1 is longer by specified SJW. If phase error is negative: Phase segment 2 is shorter by specified SJW. - The sample point of the data of the receiving node moves relatively due to the “discrepancy” in baud rate between the transmitting node and receiving node. CAN bus Bit timing CAN bus Bit timing Sync segment Sync segment Figure 14-21. Resynchronization Prop segment Prop segment If phase error is positve Phase segment 1 If phase error is negative Phase segment 1 Phase segment 2 Phase segment 2 Sample point Sample point Data bit time(DBT) R01UH0317EJ0004 Rev. 0.04 807 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.4 Connection with Target System The microcontroller incorporated a CAN has to be connected to the CAN bus using an external transceiver. Microcontroller incorporated a CAN Figure 14-22. Connection to CAN Bus CTxD CRxD Transceiver CAN_L CAN_H R01UH0317EJ0004 Rev. 0.04 808 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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