RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Figure 14-69 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 14-69. ABT Message Transmit Processing START ABTTRG = 0? Yes Set C0MDATAxm register Set C0MDLCm register Clear RTR bit of C0MCONFm register Set C0MIDLm and C0MIDHm registers END Yes Clear RDY bit RDY = 0? Set RDY bit Set all ABT transmit messages? Yes TSTAT = 0? Yes Set ABTTRG bit Caution The ABTTRG bit should be set to 1 after the TSTAT bit is cleared to 0. Checking the TSTAT bit and setting the ABTTRG bit to 1 must be processed continuously. Remark This processing (normal operation mode with ABS) can only be applied to message buffers 0 to 7. For message buffers other than the ABT message buffers, refer to Figure 14-68. R01UH0317EJ0004 Rev. 0.04 925 Feb. 22, 2013 No No No No
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Figure 14-70. Transmission via Interrupt (Using C0LOPT register) Data frame Set C0MDATAxm register Set C0MDLCm register Clear RTR bit of C0MCONFm register Set C0MIDLm and C0MIDHm registers START Transmit completion interrupt processing Read C0LOPT register Clear RDY bit RDY = 0? Data frame or remote frame? Set RDY bit END Yes Set TRQ bit Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. R01UH0317EJ0004 Rev. 0.04 926 Feb. 22, 2013 No Remote frame Set C0MDLCm register Set RTR bit of C0MCONFm register Set C0MIDLm and C0MIDHm registers Remark Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again. It is recommended to cancel any sleep mode requests, before processing TX interrupts.
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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