RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1325 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFFE6 - - - - FFFE7 - - - - FFFE8 - - - - FFFE9 - - - - FFFEA - - - - FFFEB - - - - FFFEC - - - - FFFED - - - - FFFEE - - - - FFFEF - - - - FFFF0 - - - - FFFF2 MK1 (Interrupt mask flag register 1) - - E - - - - - - - - MK1L (Interrupt mask flag register 1L) E E - E E E E E E E E TMMK03 TMMK02 TMMK01 TMMK00 SGMK PMKLR0 LSMK0 LRMK0 E E E E E E E E MK1H (Interrupt mask flag register 1H) E E - E E E E E E E E TMMK04 IICMK11 CSIMK10 PMKLR1 LSMK1 LRMK1 LTMK1 ADMK E E E E E E E E PR00 (Priority specification flag register 00) - - E - - - - - - - - PR00L (Priority specification flag register 00L) E E - E E E E E E E E PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0 E E E E E E E E PR00H (Priority specification flag register 00H) E E - E E E E E E E E LTPR00 ITPR0 RTCPR0 DMAPR01 DMAPR00 CSIPR001 CSIPR000 CLMPR0 E E E E E E E E PR01 (Priority specification flag register 01) - - E - - - - - - - - PR01L (Priority specification flag register 01L) E E - E E E E E E E E TMPR003 TMPR002 TMPR001 TMPR000 SGPR0 PPR0LR0 LSPR00 LRPR00 E E E E E E E E PR01H (Priority specification flag register 01H) E E - E E E E E E E E TMPR004 IICPR011 CSIPR010 PPR0LR1 LSPR01 LRPR01 LTPR01 ADPR0 E E E E E E E E PR10 (Priority specification flag register 10) - - E - - - - - - - - PR10L (Priority specification flag register 10L) E E - E E E E E E E E PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1 E E E E E E E E PR10H (Priority specification flag register 10H) E E - E E E E E E E E LTPR10 ITPR1 RTCPR1 DMAPR11 DMAPR10 CSIPR101 CSIPR100 CLMPR1 E E E E E E E E PR11 (Priority specification flag register 11) - - E - - - - - - - - PR11L (Priority specification flag register 11L) E E - E E E E E E E E TMPR103 TMPR102 TMPR101 TMPR100 SGPR1 PPR1LR0 LSPR10 LRPR10 E E E E E E E E PR11H (Priority specification flag register 11H) E E - E E E E E E E E TMPR104 IICPR111 CSIPR110 PPR1LR1 LSPR11 LRPR11 LTPR11 ADPR1 E E E E E E E E MDAL (Multiplication input data register A(L)) - - E - - - - - - - - MULA (Multiplication input data register A) - - E - - - - - - - - MDAH (Multiplication input data register A(H)) - - E - - - - - - - - MULB (Multiplication input data register B) - - E - - - - - - - - 1325 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1326 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFFF4 - - - - FFFF6 - - - - FFFFE MDBH (Multiplication input data register B(H)) - - E - - - - - - - - MULOH (Higher multiplication result storage register) - - E - - - - - - - - MDBL (Multiplication input data register B(L)) - - E - - - - - - - - MULOL (Lower multiplication result storage register) - - E - - - - - - - - PMC (Processor mode control register) E E - R R R R R R R E MAA - - - - - - - E 1326 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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Under development Preliminary docum
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