RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 16 LCD CONTROLLER/DRIVER (3) Output waveforms of common signals and segment signals during LCD display signal output period The voltages shown in Table 16-4 are output to the common signals and segment signals during the LCD display signal output period. When both common and segment signals are at the select voltage, a display on-voltage of VLCD is obtained. The other combinations of the signals correspond to the display off-voltage. Table 16-4. LCD Drive Voltage (a) Static display mode (during LCD display signal output period) Segment Signal Select Signal Level Deselect Signal Level Common Signal VSS/VLC0 VLC0/VSS VLC0/VSS –VLCD/+VLCD 0 V/0 V (b) 1/3 bias method (during LCD display signal output period) Segment Signal Select Signal Level Deselect Signal Level Common Signal VSS/VLC0 VLC1/VLC2 Select signal level VLC0/VSS –VLCD/+VLCD 1 1 – VLCD/+ VLCD 3 3 Deselect signal level VLC2/VLC1 1 1 – VLCD/+ VLCD 3 3 1 1 + VLCD/– VLCD 3 3 R01UH0317EJ0004 Rev. 0.04 983 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-15 shows the common signal waveforms, and Figure 16-16 shows the voltages and phases of the common and segment signals. COMn (Static display) TF = T Figure 16-15. Common Signal Waveforms (a) Static display mode T: One LCD clock period TF: Frame frequency COMn (Three-time slot mode) COMn (Four-time slot mode) TF = 3 × T TF = 4 × T (b) 1/3 bias method T: One LCD clock period TF: Frame frequency R01UH0317EJ0004 Rev. 0.04 984 Feb. 22, 2013 VLC0 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLCD VLC2 VSS VLCD VLCD
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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