RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER
15.4 Timing
This section starts with the timing of the timer counter and general output timing behaviour. This section describes the
timing at which the timer counter increments and when the count value is generally output. An example showing
automatic phase shifting is also provided.
15.4.1 Timer counter
The free running up counter is clocked by the timer count clock selected in register MCNTC0.
The counting operation is enabled or disabled by the MCNTC0.PCE bit.
CLK
CNT0
PCE
Figure 15-11. Restart Timing after Count Stop (Count Start—Count Stop—Count Start)
0H 1H 2H 7H 8H 00H
1H 2H 3H 4H
Count Start
Count Stop
Count Start
Sequence
Count Start:
– Enable counting operation (MCNTC0.PCE = 1)
– Timer counter starts with value 00H. Depending on bit MCNTC0.FULL, all following counter cycles start with
00H or 01H, respectively.
Count Stop:
– Disable counting operation (MCNTC0.PCE = 0)
– Counting is stopped and timer counter is set to 00H.
R01UH0317EJ0004 Rev. 0.04 962
Feb. 22, 2013