RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Supply voltage (VDD) VLVD LVIF flag LVIMD flag LVILV flag LVIRF flag (RESF register ) LVD reset signal POR reset signal Internal reset signal Figure 24-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) H H Cleared by software Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Cleared by software Cleared Cleared R01UH0317EJ0004 Rev. 0.04 1121 Feb. 22, 2013 Time
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR 24.4.2 When used as interrupt mode When starting operation Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD) by using the option byte 000C1H/020C1H. Start in the following initial setting state. Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) When the option byte LVIMDS1 is clear to 0 and LVIMDS0 is set to 1, the initial value of the LVIS register is set to 00H. Bit 7 (LVIMD) is 0 (interrupt mode). Bit 0 (LVILV) is 1 (low-voltage detection level: VLVD). Figure 24-5 shows the timing of the internal interrupt signal generated by the voltage detector. R01UH0317EJ0004 Rev. 0.04 1122 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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RL78/D1A User’s Manual: Hardware
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