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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 12 SERIAL ARRAY UNIT<br />

INTTM23<br />

fCLK<br />

Serial clock I/O pin<br />

(SCK10)<br />

Serial data input pin<br />

(SI10)<br />

Serial clock I/O pin<br />

(SCL11)<br />

Serial data input pin<br />

(SDA11)<br />

Peripheral enable<br />

register 0 (PER0)<br />

SAU1EN<br />

PRS<br />

113<br />

Channel 0<br />

PM133/PM51<br />

TXE<br />

10<br />

RXE<br />

10<br />

Channel 1<br />

Selector<br />

PRS<br />

112<br />

Figure 12-3. Block Diagram of Serial Array Unit 1<br />

Serial clock select register 1 (SPS1)<br />

4<br />

Edge<br />

detection<br />

DAP<br />

10<br />

PRS<br />

111<br />

Selector<br />

PRS<br />

110<br />

PRS<br />

103<br />

fCLK/2 0 - fCLK/2 11<br />

CK11 CK10<br />

Output latch<br />

(P133/P51)<br />

Edge/level<br />

detection<br />

CKP<br />

10<br />

0<br />

Prescaler<br />

CKS<br />

10<br />

PRS<br />

102<br />

4<br />

Selector<br />

CCS<br />

102<br />

PRS<br />

101<br />

PRS<br />

100<br />

fCLK/2 0 - fCLK/2 11<br />

STS<br />

100<br />

Serial mode register 10 (SMR10)<br />

0<br />

0<br />

DIR<br />

10<br />

Serial data register 10 (SDR10)<br />

SLC<br />

101<br />

SLC<br />

100<br />

Shift register<br />

Communication controller<br />

Serial data output pin<br />

(SDA11)<br />

Serial transfer end interrupt<br />

(INTIIC11)<br />

R01UH0317EJ0004 Rev. 0.04 562<br />

Feb. 22, 2013<br />

Note<br />

Serial communication operation setting register 10 (SCR10)<br />

CK11 CK10<br />

Edge/level<br />

detection<br />

Serial output register 1 (SO1)<br />

0 0 0 0 0 0 CKO11 CKO10 0 0 0 0 0 0 SO11 SO10<br />

fSCK<br />

Selector<br />

fMCK<br />

Selector<br />

Clock controller<br />

fTCLK<br />

DLS<br />

102<br />

DLS<br />

101<br />

DLS<br />

100<br />

CSI10<br />

TSF<br />

10<br />

Communication<br />

status<br />

Communication controller<br />

Mode selection<br />

IIC11<br />

BFF<br />

10<br />

0 0 SE11 SE10<br />

0 0 SS11 SS10<br />

0 0 ST11 ST10<br />

0 0 SOE11 SOE10<br />

0 0 SOL11 SOL10<br />

Output latch<br />

(P131/P53)<br />

FECT<br />

10<br />

Interrupt<br />

controller<br />

Serial flag clear trigger<br />

register 10 (SIR10)<br />

FEF<br />

10<br />

Output<br />

controller<br />

PECT<br />

10<br />

Error controller<br />

PEF<br />

10<br />

OVCT<br />

10<br />

OVF<br />

10<br />

Serial status register 10 (SSR10)<br />

PM131/PM53<br />

Clear<br />

Error<br />

information<br />

Serial channel enable<br />

status register 1 (SE1)<br />

Serial channel start<br />

register 1 (SS1)<br />

Serial channel stop<br />

register 1 (ST1)<br />

Serial output enable<br />

register 1 (SOE1)<br />

Serial output level<br />

register 1 (SOL1)<br />

Serial data output pin<br />

(SO10)<br />

Serial transfer end interrupt<br />

(INTCSI10)<br />

Note When operation is stopped (SEmn = 0), the higher 7 bits become the clock division setting section and the lower<br />

bits are fixed to 0.<br />

During operation (SEmn = 1), it becomes a buffer register.

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