RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT CHAPTER 12 SERIAL ARRAY UNIT 48 pin 64 pin 80 pin 100 pin R5F10CGx /R5F10DGx R5F10CLx /R5F10DLx R5F10CMx /R5F10DMx R5F10TPx /R5F10DPx CSI 2 channel 3 channel Simplified I 2 C 1 channel The serial array unit has two serial channels per unit and can use two or more of various serial interfaces (3-wire serial (CSI), and simplified I 2 C) in combination. Function assignment of each channel supported by the RL78/D1A is as shown below. 0 1 Unit Channel Used as CSI Used as Simplified I 2 C 0 CSI00 1 CSI01 0 CSI10 1 IIC11 R01UH0317EJ0004 Rev. 0.04 557 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.1 Functions of Serial Array Unit 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10) This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] Data length of 7 to 16 bits Phase control of transmit/receive data MSB/LSB first selectable Level setting of transmit/receive data [Clock control] Master/slave selection Phase control of I/O clock Setting of transfer period by prescaler and internal counter of each channel [Interrupt function] Transfer end interrupt/buffer empty interrupt [Error detection flag] Overrun error 12.1.2 Simplified I 2 C (IIC11) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I 2 C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master and does not have a function to detect wait states. Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop conditions are observed. [Data transmission/reception] Master transmission, master reception (only master function with a single master) ACK output function Note and ACK detection function Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) Manual generation of start condition and stop condition [Interrupt function] Transfer end interrupt [Error detection flag] Overrun error Parity error (ACK error) * [Functions not supported by simplified I 2 C] Slave transmission, slave reception Arbitration loss detection function Wait detection functions Note An ACK is not output when the last data is being received by writing 0 to the SOEmn (SOEm register) bit and stopping the output of serial communication data. See 12.8.3 (2) Processing flow for details. R01UH0317EJ0004 Rev. 0.04 558 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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