RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (4/6)
(6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register CSC Register Oscillation accuracy CKC Register
Status Transition HIOSTOP
stabilization time
MCM0
(C) (B) 0 30 s 0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
Status Transition
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CSC Register Waiting for Oscillation CKC Register
XTSTOP
Stabilization
CSS
(C) (D) 0 Necessary 1
Unnecessary if the CPU is operating with the
subsystem clock
(8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CSC Register CKC Register
Status Transition HIOSTOP CSS MCM0
(D) (B) 0 0 0
Unnecessary if the CPU
is operating with the
high-speed on-chip
oscillator clock
Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
Unnecessary if this
register is already set
R01UH0317EJ0004 Rev. 0.04 306
Feb. 22, 2013