RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS
Type Default
priority
Note
Table 20-1. Interrupt Source List (2/2)
Interrupt Source
Name Trigger
Internal
/External
Vector
table
address
Mask 35 INTC1ERR CAN1 error interrupt Internal 0004AH (A) – – – – – – –
able
36 INTC1WUP CAN1 wakeup Internal 0004CH – – – – – – –
37 INTC0ERR CAN0 error interrupt Internal 0004EH – – –
38 INTC0WUP CAN0 wakeup Internal 00050H – – –
39 INTC0REC CAN0 reception completion Internal 00052H – – –
40 INTC0TRX CAN0 transmission completion Internal 00054H – – –
41 INTTM10 End of TAU 10 count or capture interrupt Internal 00056H
42 INTTM11 End of TAU 11 count or capture interrupt Internal 00058H
43 INTTM12 End of TAU 12 count or capture interrupt Internal 0005AH
44 INTTM13 End of TAU 13 count or capture interrupt Internal 0005CH
45 INTMD End of division operation/Overflow occur Internal 0005EH
46 INTC1REC CAN1 reception completion Internal 00060H – – – – – – –
47 INTFL End of sequencer interrupt(Flash programming) Internal 00062H
48 INTC1TRX CAN1 transmission completion Internal 00064H – – – – – – –
49 INTTM14 End of TAU 14 count or capture interrupt Internal 00066H
50 INTTM15 End of TAU 15 count or capture interrupt Internal 00068H
51 INTTM16 End of TAU 16 count or capture interrupt Internal 0006AH
52 INTTM17 End of TAU 17 count or capture interrupt Internal 0006CH
53 INTTM20 End of TAU 20 count or capture interrupt Internal 0006EH
54 INTTM21 End of TAU 21 count or capture interrupt Internal 00070H
55 INTTM22 End of TAU 22 count or capture interrupt Internal 00072H
56 INTTM23 End of TAU 23 count or capture interrupt Internal 0074H
57 INTTM24 End of TAU 24 count or capture interrupt Internal 0076H
58 INTTM26 End of TAU 26 count or capture interrupt Internal 0078H
59 INTDMA2 End of DMA2 transfer Internal 007AH – – – – – –
60 INTDMA3 End of DMA3 transfer Internal 007CH – – – – – –
Soft
ware
- BRK Execution of BRK instruction - 007EH (C)
Reset - RESET RESET pin input - 0000H -
POR Power-on-reset
LVD Voltage detectionNote
WDT Overflow of watchdog timer
TRAP Execution of illegal instruction
IAW Illegal-memory access
RPE RAM parity error
Note The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously.
Zero indicates the highest priority and 60 indicates the lowest priority.
R01UH0317EJ0004 Rev. 0.04 1051
Feb. 22, 2013
Basic Configuration
type
R5F10CGx
R5F10DGx
R5F10CLx
R5F10DLx
R5F10CMx
R5F10DMx
R5F10DPx/
R5F10TPJ
R5F10DPJ