RL78/D1A User's Manual: Hardware - Renesas

Operation is resumed.
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
Figure 6-66. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit, TAU1EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 to CKm3.
Sets the TMRmn register (determines operation mode of
channel).
Sets TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
The TDRmn register can always be read.
The TCRmn register can always be read.
The TSRmn register can always be read.
Set values of TOMmn, TOLmn, TOmn, and TOEmn bits
cannot be changed.
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TAU stop The TAU0EN bit, TAU1EN bit of the PER0 register are
cleared to 0.
Remark m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and count operation starts.
TCRmn is cleared to 0000H at the count clock input.
When the MDmn0 bit of the TMRmn register is 1,
INTTMmn is generated.
Counter (TCRmn) counts up from 0000H. When the TImn
pin input valid edge is detected, the count value is
transferred (captured) to TDRmn. At the same time,
TCRmn is cleared to 0000H, and the INTTMmn signal is
generated.
If an overflow occurs at this time, the OVF bit of the
TSRmn register is set; if an overflow does not occur, the
OVF bit is cleared.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
TCRmn holds count value and stops.
The OVF bit of the TSRmn register is also held.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
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Feb. 22, 2013