RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 24 VOLTAGE DETECTOR
When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 µs
or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0)
clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the LVIMD
bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD.
Figure 24-8. shows the procedure for initial setting of interrupt and reset mode.
No
Figure 24-8. Initial Setting of Interrupt and Reset Mode
Power supply started
Reset source
determined
LVIRF = 1 ?
Yes
LVISEN = 1
Voltage detection
stabilization wait time
LVIMD = 0
LVISEN = 0
Normal operation
Remark fIL: Low-speed on-chip oscillator clock frequency
Refer to Figure 24-9. Checking reset source.
Check internal reset generation by LVD circuit
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
Count 400 µs or 5 clocks of fIL by software.
Set the LVIMD bit to 0 to set interrupt mode.
Set the LVISEN bit to 0 to enable voltage detection.
R01UH0317EJ0004 Rev. 0.04 1130
Feb. 22, 2013